Analysis of Soft Error Rate in Flip - Flops and Scannable Latches

the critical charge by increasing the gate capacitance while errors are gaining importance as technology scales. Flip-flops, an important component of pipelined architectures, are becoming more susceptible to soft errors. This work analyzes soft error rates on a variety of flip-flops. The analysis was performed by implementing and simulating the various designs in 70 nm, 1V CMOS technology. First, we evaluate the critical charge for the susceptible nodes in each design. Further, we implement two hardening techniques and present the results. One attempts to increase the other improves the overall robustness of the circuit by replicating the master stage of the master slave flip-flops, which leads to reduced power and area overhead. I. INTRODUCTION oft errors pose a major challenge for the continued scaling of CMOS circuits. They result due to the excess charge carriers induced primarily by external radiations. The circuit however is not permanently damaged by such radiations. The rapid technology scaling has accelerated the reduction in the capacitance of storage nodes and supply voltages thus resulting in increased susceptibility of latches and flip-flops to soft errors. These circuits are more difficult to protect than memories by conventional logic methods like parity and error correcting codes. Also as frequency increases, the probability of a flip-flop to latch on to an error increases [7]. So analysis of traditional flip-flop designs for soft error rates and improvising them for protection against soft errors is of paramount importance. In this paper, we present a detailed analysis of effect of soft errors in different styles of flip-flops designed in 70nm, 1V CMOS technology. A variety of flip-flop designs are analyzed and evaluated for critical charge on the susceptible nodes. Earlier work on soft errors has focused on quantifying the circuit susceptibility radiations in terms of the critical charge required to charge or discharge a particular node and the sensitive node area [l]. Various methods for reducing soft error rate (SER) in deep sub-micron integrated circuits were discussed in [2]. Further soft error tolerant techniques like space and time redundancy were proposed [3]. Initially most of the work on soft errors focused on SRAM and DRAM memory cells as they are more susceptible to soft errors. But